1. Murthy, S., Verma, U.: Designed 32-bit RISC CPU based on DLX architecture. In: ICCUBEA, Pune, India. IEEE (2015)
2. Ritupurkar, S.P., Thakare, M.N., Korde, G.D.: RISC CPU based on MIPS using VHDL. In: ICACCS, Coimbatore, India. IEEE (2015)
3. Joseph, N., Sabarinath S.: FPGA based implementation of high performance architectural level low power 32-bit RISC core. IEEE (2009)
4. Kelgaonkar, P.S., Kodgire, S.: Designed 32-bit pipelined RISC on Spartan-6. IEEE (2016)
5. Ajith Kumar, P., Vijaya Lakshmi, M.: Design of a pipelined 32-bit MIPS processor with floating point unit. Int. J. Innov. Res. Sci. Eng. Technol. 5(7) (2016). ISSN 2319-8753