1. Dakua, P.K., Sinha, A., Shivdhari & Gourab: Hardware implementation of MAC unit. Int. J. Electron. Commun. Comput. Eng. 3(1), 79–82 (2012)
2. Li, Y., Chen, J.: A reconfigurable architecture of a high performance 32-bit MAC unit for embedded DSP. In: Proceedings of 5th International Conference on Semiconductor Manufacturing, ASIC 2003, vol. 2, pp. 1285–1288 (2003)
3. Gurjar, P., Solanki, R., Kansilwal, P., Vucha, M.: VLSI implementation of adders for high speed ALU. In: 2011 Annual IEEE India Conference India Conference (INDICON), 1–6 December 2011. IEEE (2011)
4. Kamboh, H.M., Khan, S.A.: FPGA implementation of fast adder. In: 7th International Conference on Computing and Convergence Technology (ICCCT), pp. 1324–1327 (2012)
5. Wallace, C.S.: A suggestion for a fast multiplier. IEEE Trans. Electron. Comput. EC-13(1), 14–17 (1964). https://doi.org/10.1109/PGEC.1964.263830