High Sensitivity Optical Receiver Architecture
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-97-0881-9_7
Reference4 articles.
1. Y. Kwon, S. Park, T. Park, K. Cho, H. Lee, An ultra low-power CMOS transceiver using various low-power techniques for LR-WPAN applications. IEEE Trans. Circuits Syst. I: Reg. Papers 59(2), 324–336 (2012)
2. L.B. Oliveira, C.M. Leitao, M.M. Silva, Noise performance of a regulated cascode transimpedance amplifier for radiation detectors. IEEE Trans. Circuits Syst. I: Reg. Papers 59(9), 1841–1848 (2012)
3. M. Atef, H. Zimmermann, Optical receiver using noise cancelling with an integrated photodiode in 40 nm CMOS technology, in Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 7, pp. 1929–1936, July 2013
4. S. Chu et al., A 22 to 26.5 Gb/s optical receiver with all-digital clock and data recovery in a 65 nm CMOS process. IEEE J. Solid-State Circuits 50(11), 2603–2612 (2015)
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