256-Bit AES Encryption Using SubBytes Blocks Optimisation
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-7954-7_56
Reference9 articles.
1. Sharma RK, Rajeswara Rao M (2017) FPGA implementation of combined S-box and InvS-box of AES. In: 2017 4th international conference on signal processing and integrated networks (SPIN)
2. Iyer NC, Anandmohan PV, Poornaiah DV (2010) Mix/InvMixColumn decomposition and resource sharing in AES
3. Parhi KK, Zhang X (2004) High speed VLSI designs for the AES algorithm. IEEE 12(9)
4. Kumar A, Shaik F, Rahim BA, Kumar DS (2016) Signal and image processing in medical applications. Springer, Heidelberg. https://doi.org/10.1007/978-981-10-0690-6
5. Stallings W (2007) Data and computer communications. Pearson Education India
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