Negative Capacitance Field-Effect Transistor (NCFET): Strong Beyond CMOS Device
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-97-4623-1_8
Reference27 articles.
1. Amrouch H, Pahwa G, Gaidhane AD, Henkel J, Chauhan YS (2018) Negative capacitance transistor to address the fundamental limitations in technology scaling: processor performance. IEEE Access 6:52754–52765. https://doi.org/10.1109/ACCESS.2018.2870916
2. Bheemana RC, Japa A, Yellampalli SS, Vaddi R (2022) Negative capacitance FETs for energy efficient and hardware secure logic designs. Microelectronics J 119(November):105320. https://doi.org/10.1016/j.mejo.2021.105320
3. Bhushan B, Nayak K, Rao VR (2012) DC compact model for SOI tunnel field-effect transistors. IEEE Trans Electron Devices 59(10):2635–2642. https://doi.org/10.1109/TED.2012.2209180
4. Dasgupta A et al (2020) BSIM compact model of quantum confinement in advanced nanosheet FETs. IEEE Trans Electron Devices 67(2):730–737. https://doi.org/10.1109/TED.2019.2960269
5. Duarte JP et al (2017) Compact models of negative-capacitance FinFETs: Lumped and distributed charge models. In: Technical Digital International Electron Devices Meeting IEDM, pp 30.5.1–30.5.4. https://doi.org/10.1109/IEDM.2016.7838514
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