Design and Implementation of Logarithmic Multiplier Using FinFETs for Low Power Applications
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Publisher
Springer Singapore
Link
http://link.springer.com/content/pdf/10.1007/978-981-13-5802-9_78
Reference11 articles.
1. Babić Z, Avramović A, Bulić P (Feb 2011) An iterative logarithmic multiplier. Microprocess Microsyst 35(1):23–33. https://doi.org/10.1016/j.micpro.2010.07.001
2. Fahad HM, Hu C, Hussain MM (Jan 2015) Simulation study of a 3-d device integrating FinFET and UTBFET. IEEE Trans Electron Devices 62(1):83–87. https://doi.org/10.1109/ted.2014.2372695
3. Guo D, Shang H, Seo K, Haran B (Oct 2014) 10 nm FINFET technology for low power and high performance applications. In: 2014 12th IEEE international conference on solid-state and integrated circuit technology (ICSICT). IEEE. https://doi.org/10.1109/icsict.2014.7021207
4. Havaldar D, Katti G, DasGupta N, DasGupta A (April 2006) Subthreshold current model of FinFETs based on analytical solution of 3-d poisson’s equation. IEEE Trans Electron Devices 53(4):737–742. https://doi.org/10.1109/ted.2006.870874
5. Jurczak M, Collaert N, Veloso A, Hoffmann T, Biesemans S (Oct 2009) Review of FINFET technology. In: 2009 IEEE international SOI conference. IEEE. https://doi.org/10.1109/soi.2009.5318794
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