Author:
Nagajyothi Grande,Kumar G. Pavan,Kumar Budati Suresh,Kumar B. P. Deepak,Damodaram A. K.
Publisher
Springer Nature Singapore
Reference7 articles.
1. A. Aggarwal et al., Optimal design of 2D FIR filters with quadrantally symmetric properties using fractional derivative constraints. Circ. Syst. Signal Process. 35(6), 2213–2257 (2016)
2. A. Chandra, S. Chattopadhyay, Design of hardware efficient FIR filter: a review of the state-of-the-art approaches. Eng. Sci. Technol. Int. J. 19(1), 212–226 (2016)
3. A.P. Chavan, R. Verma, N.S. Bhat, High speed 32-bit Vedic multiplier for DSP applications. Int. J. Comput. Appl. 135(7), 35–38 (2016). Published by Foundation of Computer Science (FCS)
4. A. Garg, G. Joshi, Gate diffusion input based 4-bit Vedic multiplier design. IET Circ. Dev. Syst. 12(6), 764–770 (2018)
5. P.A.I. Khan, S.K. Dilshad, B.K. Sree, Design of 2 × 2 Vedic multiplier using GDI technique, in 2017 International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS) (IEEE, 2017)
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2 articles.
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