Author:
Patra Sumit,Kumar Sunil,Verma Swati,Kumar Arvind
Reference10 articles.
1. David, A.P., John, L.H.: Computer Organization and Design: The Hardware/Software Interface, vol. 1, p. 998. San mateo, CA: Morgan Kaufmann Publishers (2005)
2. Palnitkar, S.: Verilog HDL: A Guide to Digital Design and Synthesis, vol. 1. Prentice Hall Professional (2003)
3. Topiwala, M.N., Saraswathi, N.: Implementation of a 32-bit MIPS based RISC processor using Cadence. In: 2014 International Conference on Advanced Communication Control and Computing Technologies (ICACCCT). IEEE (2014)
4. Kadam, S.U., Mali, S.D.: Design of risc processor using VHDL. 2016 Int. J. Res. Granthaalaya 4(6) (2016)
5. Oliver, J.P., et al.: Clock gating and clock enable for FPGA power reduction. In: 2012 VIII Southern Conference on Programmable Logic (SPL). IEEE (2012)
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