Analysis of Dynamic Scheduling Algorithm for Reconfigurable Architecture
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Publisher
Springer Singapore
Link
http://link.springer.com/content/pdf/10.1007/978-981-15-7961-5_61
Reference23 articles.
1. Cai X, Hu W, Ma T, Ma R (2018) A hybrid scheduling algorithm for reconfigurable processor architecture. In: 13th IEEE conference on industrial electronics and applications (ICIEA), June 2018. https://doi.org/10.1109/iciea.2018.8397812
2. Park H-W, Kim W, Yoo D, Ryu S, Kim J (2013) A scalable scheduling algorithm for coarse-grained reconfigurable architecture. In: IEEE international conference on consumer electronics (ICCE), March 2013. https://doi.org/10.1109/icce.2013.6487011
3. Noguera J, Badia RM (2002) HW/SW codesign techniques for dynamically reconfigurable architectures. IEEE Trans Very Large Scale Integr (VLSI) Syst 10(4):399–415
4. Ka C-C (2015) Performance-oriented partitioning for task scheduling of parallel reconfigurable architectures. IEEE Trans Parallel Distrib Syst 26(3):858–867
5. Popp A, Moullec YL, Koch P (2009) Scheduling temporal partitions in a multiprocessing paradigm for reconfigurable architectures. In: NASA/ESA conference on adaptive hardware and systems, November 2009. 10.1109/AHS.2009.43
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