Design and Implementation of Adders and Multipliers for DSP Applications
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-7137-4_6
Reference23 articles.
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3. Yezerla SK, Rajendra Naik B (2014) Design and estimation of delay, power and area for Parallel prefix adders. Recent Adv Eng Comput Sci (RAECS), pp 1–6. https://doi.org/10.1109/RAECS.2014.6799654
4. Maurya KAK, Lakshmanna YR, Sindhuri KB, Kumar NU (2017) Design and implementation of 32-bit adders using various full adders. Innov Power Adv Comput Technol (i-PACT), pp 1–6. https://doi.org/10.1109/IPACT.2017.8245176
5. SP, Khan AA (2018) Comparison of Braun multiplier and Wallace multiplier techniques in VLSI. In: 4th International conference on devices, circuits and systems (ICDCS), pp 48–53. https://doi.org/10.1109/ICDCSyst.2018.8605173
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