All Digital Phase Locked Loop (ADPLL) and Its Blocks—A Comprehensive Knowledge

Author:

Yadav Lalita,Duhan Manoj

Publisher

Springer Nature Singapore

Reference35 articles.

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2. Yang, J., Zhang, Z., Nan QI, Liu, L., Liu J., Wu, N.: A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase-locked loop with fine frequency tuning circuits. Sci. China Inf. Sci. 62(6), 1–16 (2019)

3. Best, R.E.: Phase-Locked Loops: Design, Simulation & Applications, 4th edn. McGraw-Hill Professional Engineering (1999)

4. Introduction to FPGA based ADPLLs. Silicon Labs (2011)

5. Chen, F.T., et al.: A 10-Gb/s low jitter single-loop clock and data recovery circuit with rotational phase frequency detector. IEEE Trans. Circuits Syst. I Regul. Pap. 61(11), 3278–3287 (2014)

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