Design and Implementation of Multi-bit Self-checking Carry Select Adder

Author:

Kavitkar Shivkumar,Anita Angeline A.

Publisher

Springer Singapore

Reference7 articles.

1. Vasudevan DP, Lala PK, Pakerson JP (2014) Self-checking carry-select adder design based on two-rail encoding. IEEE Trans Circ Syst (i: regular papers) 61(7)

2. “1965 Moore’s law predicts the future of integrated circuits”. Computer History Museum 2007

3. Wang MC (2009) Low power, area efficient FinFET circuit design. In: Proceedings of the world congress on engineering and computer science 2009, vol I, WCECS 2009, 20–22 Oct 2009, San Francisco, USA

4. Akbar MA, Lee J-A (2013) Self-checking carry select adder with fault Localization. In: 16th Euromicro conference on digital system design

5. Ramkumar B, Kittur HM (2012) Low-power and area-efficient carry select adder. IEEE Trans Very Large Scale Integr (VLSI) Syst 20(2)

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1. Design and implementation of high-speed and low-power consumption Moore-based loopback adder on FPGA;International Journal of Intelligent Unmanned Systems;2021-02-18

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