A Customized Hardware Architecture for Multi-layer Artificial Neural Networks on FPGA-Reference-Cited by-同舟云学术

A Customized Hardware Architecture for Multi-layer Artificial Neural Networks on FPGA

Published:2018 Issue: Volume: Page:637-644
ISSN:2194-5357
Container-title:Advances in Intelligent Systems and Computing
language:
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Author:

Vu Huynh Minh,Thang Huynh Viet

Publisher

Springer Singapore

Link

http://link.springer.com/content/pdf/10.1007/978-981-10-7512-4_63

Reference10 articles.

1. J. Misra and I. Saha, “Artificial neural networks in hardware: A survey of two decades of progress,” Neurocomputing, vol. 74, no. 1–3 (2010) 239–255.

2. N. Nedjah, R. M. da Silva, and L. de Macedo Mourelle, “Compact yet efficient hardware implementation of artificial neural networks with customized topology,” Expert Syst. Appl., vol. 39, no. 10 (2012) 9191–9206.

3. T. V. Huynh, “Design space exploration for a single-FPGA handwritten digit recognition system,” in 2014 IEEE Fifth International Conference on Communications and Electronics (ICCE), (2014) 291–296.

4. T. V. Huynh, “Design of Artificial Neural Network Architecture for Handwritten Digit Recognition on FPGA,” J. Sci. Technology, UDN, vol. 108 (2016) 206–210.

5. J. Park and W. Sung, “FPGA based implementation of deep neural networks using on-chip memory only,” in 2016 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) (2016) 1011–1015.

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