1. Hedler, H., T. Meyer, and B. Vasquez, “Transfer wafer level packaging,” US Patent 6,727,576, filed on Oct. 31, 2001; patented on April 27, 2004.
2. Lau, J. H., “Patent Issues of Fan-Out Wafer/Panel-Level Packaging”, Chip Scale Review, Vol. 19, November/December 2015, pp. 42–46.
3. Brunnbauer, M., E. Furgut, G. Beer, T. Meyer, H. Hedler, J. Belonio, E. Nomura, K. Kiuchi, and K. Kobayashi, “An Embedded Device Technology Based on a Molded Reconfigured Wafer”, IEEE/ECTC Proceedings, May 2006, pp. 547–551.
4. Brunnbauer, M., E. Furgut, G. Beer, and T. Meyer, “Embedded Wafer Level Ball Grid Array (eWLB)”, IEEE/EPTC Proceedings, May 2006, pp. 1–5.
5. Keser, B., C. Amrine, T. Duong, O. Fay, S. Hayes, G. Leal, W. Lytle, D. Mitchell, and R. Wenzel, “The Redistributed Chip Package: A Breakthrough for Advanced Packaging”, Proceedings of IEEE/ECTC, May 2007, pp. 286–291.