2D, 2.1D, and 2.3D IC Integration

Author:

Lau John H.

Publisher

Springer Singapore

Reference62 articles.

1. Lau, J. H., P. Tzeng, C. Lee, C. Zhan, M. Li, J. Cline, K. Saito, Y. Hsin, P. Chang, Y. Chang, J. Chen, S. Chen, C. Wu, H. Chang, C. Chien, C. Lin, T. Ku, R. Lo, and M. Kao, “Redistribution Layers (RDLs) for 2.5D/3D IC Integration”, IMAPS Transactions, Journal of Microelectronic Packaging, Vol. 11, No. 1, First Quarter 2014, pp. 16–24.

2. Lau, J. H., “8 Ways to Make RDLs for FOW/PLP”, Chip Scale Review, Vol. 22, May/June 2018, pp. 11–19.

3. Lau, J. H., “Redistribution-Layers for Heterogeneous Integrations”, Chip Scale Review, Vol. 23, January/February 2019, pp. 20–25.

4. Kripesh, V., V. Rao, A. Kumar, G. Sharma, K. Houe, X. Zhang, K. Mong, N. Khan, and J. H. Lau, “Design and Development of a Multi-Die Embedded Micro Wafer Level Package”, IEEE/ECTC Proceedings, 2008, pp. 1544–1549.

5. Khong, C., A. Kumar, X. Zhang, S. Gaurav, S. Vempati, V. Kripesh, J. H. Lau, and D. Kwong, “A Novel Method to Predict Die Shift During Compression Molding in Embedded Wafer Level Package”, IEEE/ECTC Proceedings, 2009, pp. 535–541.

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