Author:
Jijina G. O.,Mohana Priya R.,Solainayagi P.
Reference17 articles.
1. Ghamkhari SF, Ghaznavi-Ghoushchi MB (2012) A low-power low-area architecture design for distributed arithmetic (DA) unit. In: 20th Iranian conference on electrical engineering, (ICEE2012), pp 232–237
2. Mohanty BK, Meher PK (2013) A high-performance energy-efficient architecture for FIR adaptive filter based on new distributed arithmetic formulation of block LMS algorithm. IEEE Trans Signal Process 61(4):921–932
3. Meher PK, Chandrasekaran S, Amira A (2008) FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic. IEEE Trans Signal Process 56(7):3009–3017
4. Meher PK, Park SY (2011) High-throughput pipelined realization of adaptive FIR filter based on distributed arithmetic. In: 2011 IEEE/IFIP 19th international conference on VLSI and system-on-chip, pp 428–433
5. Sudhakar V, Murthy NS, Anjaneyulu L (2012) Area efficient pipelined architecture for realization of FIR filter using distributed arithmetic. In: International conference on industrial and intelligent information (ICIII 2012) IPCSIT, vol 31
Cited by
4 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献