Demodulation of 8PSK Signal with Gardner Bit Synchronization Using FPGA
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Publisher
Springer Singapore
Link
http://link.springer.com/content/pdf/10.1007/978-981-10-6571-2_81
Reference6 articles.
1. Gardner, F.M.: A BPSK/QPSK timing-error detector for sampled data receivers. IEEE Trans. Commun. COM-32, 423–429 (1986)
2. Gardner, F.M.: Interpolation in digital modems—Part I: Fundamentals. IEEE Trans. Commun. 41(3), 501–507 (1993)
3. Erup, L., Gardner, F.M., Harris, R.A.: Interpolation in digital modems—Part II: Implementation and performance. IEEE Trans. Commun. 41, 998–1008 (1993)
4. Chen, Q., Li, M.: Modified gardner algorithm for bit synchronization in high-order QAM system. In: 2013 International Conference on Computational Problem-solving (ICCP), 26–28 October 2013, pp. 427–432 (2013)
5. Hua, J., Zhou, L., Chen, C., Jiang, L.: Synchronization for QDPSK—Costas loop and Gardner algorithm using FPGAs. In: 2014 IEEE/ACIS 13th International Conference on Computer and Information Science (ICIS), 4–6 June 2014, pp. 27–31 (2014)
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1. A Carrier-Based Gardner Timing Synchronization Algorithm for BPSK Signal in Maritime Communication;Journal of Marine Science and Engineering;2023-04-13
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