1. Jaydeep, P. K., John, K., Kyung-Hoae, K., Satyanand, N., Zheng, Guo., Eric, K., Kevin, Z.: 5.6 Mb/mm2 1R1 W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology. IEEE Journal of Solid-State Circuits. vol. 52, issue. 1, pp. 229–239, (2017).
https://doi.org/10.1109/jssc.2016.2607219
.
2. Innocent Agbo., Mottaqiallah Taouil., Daniël Kraak., Said Hamdioui., Halil Kükner., Pieter Weckx., Praveen Raghavan., Francky Catthoor.: Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. vol. PP, issue: 99, pp. 1–11, (2017).
3. Liang Wen, Xu Cheng, Keji Zhou, Shudong Tian, and Xiaoyang Zeng.: Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier. IEEE Transactions on circuits and systems-II, Express Briefs, vol. 63, no. 7, pp. 643–647, (2016).
4. Balakrishna, K., Srinivasulu, A., Sarada, M.: 7-T single end and 8-T differential dual-port SRAM memory cells. IEEE Conference on Information and Communication Technologies (IEEE ICT-2013), Kumaracoil, India, Apr 11-12, pp. 1243–1246, (2013).
https://doi.org/10.1109/cict.2013.6558291
.
5. M. R. Garg, Anu Tonk, “A study of different types of voltage & current sense amplifiers used in SRAM”, International Journal of Advanced Research in Computer and Communication Engineering, vol. 4, Issue. 5, pp. 30–35, (2015).