Author:
Wahab Aeizaal Azman A.,Alhady Syed Sahal Nazli,Othman Wan Amir Fuad Wajdi,Husin Hazmarini,Adnan Nur Qamarina Muhammad
Reference9 articles.
1. Kaushik, S., Zorian, Y.: Embedded memory test and repair optimizes SoC yield in. http://www.edn.com. 17th July 2012
2. Mohammed, B.: Embedded memory interface logic and interconnect testing. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23(9), 1946–1950 (2015)
3. Mishra, D.K., Solanki, R.: Implementation of BIST architecture for testing SRAM cell using dynamic supply current. In: IRF International Conference, Bengaluru, June 2014, pp. 27–32 (2014)
4. Joseph, P.E., Antony P.R.: VLSI design and comparative analysis of memory BIST controllers. In: First International Conference on Computational Systems and Communications, Trivandrum, 17–18 December 2014 (2014)
5. Ramana Kumari, K.L.V., Asha Rani, M., Balaji, N.: FPGA implementation of memory design and testing. In: IEEE 7th International Advance Computing Conference (IACC) (2017)