Variable Resolution Time Multiplexed Digital Architecture of ADCs for System on Chip Applications
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-16-7985-8_96
Reference10 articles.
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3. Furuta M, Itakura T, Komukai S (2015) Trends in the design of high-speed, low-power analog-to-digital converters. In: IEEE international symposium on radio frequency integration technology, pp 169–171
4. Kurchuk M, Tsividis Y (2010) Signal-dependent variable-resolution clockless A/D conversion with application to continuous-time digital signal processing. IEEE Trans Circuits Syst I Regul Pap 57(5):982–991
5. Sun L, Ko C-T, Pun K-P (2014) Optimizing the stage resolution in pipelined SAR ADCs for high-speed high-resolution applications. IEEE Trans Circuits Syst II Express Briefs 61(7):476–480
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