Implementation of 64-Bit Inexact Speculative Half Unit Biased Floating-Point Adder
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-1588-0_39
Reference12 articles.
1. Hormigo J, Villalba J (2016) New formats for computing with real-numbers under round- to-nearest. IEEE Trans Comput 65(7):2158–2168
2. Ramesh S, Saravanavel K (2021) HUB floating-point adder using double path. Int J Scientif Res Sci Technol (IJSRST) 9(1):708–717
3. Shaik A, Fairooz SK (2020) HUB floating-point addition using unbiased rounding. IOSR J VLSI and Signal Process (IOSR-JVSP) 10(1):09–14
4. Lahari M, Agrawal S (2020) Efficient floating-point HUB Adder For FPGA. In: 2020 4th international conference on electronics, materials engineering and nano-technology (IEMENTech), Kolkata, India
5. Villalba-Moreno J, Hormigo J, González-Navarro S (2018) Unbiased rounding for HUB floating-point addition. IEEE Trans Comput 67(9):1359–1365
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