Author:
Goyal Candy,Singh Ubhi Jagpal,Raj Balwinder
Reference13 articles.
1. Kumar, P., Sharma, R.K.: A new energy efficient full adder design for arithmetic applications. In: 4th International Conference on Signal Processing and Integrated Networks (SPIN), pp. 555–560 (2017)
2. Park, J.C., Mooney, V.J.: Sleepy stack leakage reduction. IEEE Trans. Very Large Scale Integr. Syst. 14(11), 1250–1263 (2006)
3. Jiao, H., Kursun, V.: Reactivation noise suppression with sleep signal slew rate modulation in MTCMOS circuits. IEEE Trans. Very Large Scale Integr. Syst. 21(3), 533–545 (2013)
4. Kim, K., Nan, H., Choi, K.: Ultra low-voltage power gating structure using low threshold voltage. Int. Conf. Circuits Syst. II; Express Briefs 56(12), 926–930 (2009)
5. Parameshwara, M.C., Srinivasaiah, H.C.: Low power hybrid 1-bit full adder circuit for energy efficient arithmetic applications. J. Circuits Syst. Comput. 26(1), 1750014–1750029 (2017)