Design and Analysis of Low-Power SRAM
Author:
Publisher
Springer Singapore
Link
http://link.springer.com/content/pdf/10.1007/978-981-15-6840-4_4
Reference15 articles.
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3. Nath Mandal D et al (2014) Analysis and design of low voltage low power dynamic comparator with reduced delay and power. Int J Eng Res Gen Sci 2
4. Babayan-Mashhadi S, Lotfi R (2014) Analysis and design of a low-voltage low-power double-tail comparator. IEEE Tran Very Large Scale Integr (VLSI) Syst 22(2):343–352
5. Ay Suat U (2011) A sub-1 Volt 10-bit supply boosted SAR ADC design in standard CMOS. Analog Integr Circ Sig Process 66(2):213–221
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