Author:
Elangovan M.,Ranjith R.,Devika S.
Reference15 articles.
1. Mehrabani YS, Eshghi M (2016) Noise and process variation tolerant, low-power, high-speed and low energy full adders in CNTFET technology. IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2. Bhaskar A, Reddy D, Sarananan S, Naidu J (2016) A low power and high speed 10 transistor full adder using multi threshold technique. In: 11th international conference on industrial and information systems, pp 371–374
3. Agrawal K, Shilpa R, Kottilingel R, Sonukusare M, Rathod SS (2014) Performance characteristics of a single walled carbon nanotube field effect transistor (SWCNT-FET). In: International Conference on circuits Systems, Communication and Information Technology Applications(CSCITA)
4. Gautam H, Bindra P (2015) Structure and a detailed analysis of various simulation results of CNTFET: a review. Int J Sci Eng Technol 4(2)
5. Yadav AK, Bhavana PS, Dadoriya AK (2017) Low power high speed 1-bit full adder circuit design at 45 nm CMOS technology. In: Proceeding international conference on recent innovations is signal processing and embedded systems (RISE-2017), pp 427–432
Cited by
4 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献