Author:
Nagaraju Mamidi,Gupta Santosh Kumar,Bhadauria Vijaya,Shukla Devarshi
Reference15 articles.
1. Sullivan GJ, Ohm J-R, Han W-J, Wiegand T (2012) Overview of the high efficiency video coding (HEVC) standard. IEEE Trans Circ Syst Video Technol 22(12):1649–1668
2. Zheng, J, Lu C, Guo J, Chen D, Guo D (2019) A hardware efficient block matching algorithm and its hardware design for variable block size motion estimation in ultra-high-definition video encoding. ACM Trans Des Autom Electron Syst (TODAES) 24(2)15:1–21
3. Jia L, Tsui C-Y, Au OC, Jia K (2018) A low-power motion estimation architecture for HEVC based on a new sum of absolute difference computation. IEEE Trans Circ Syst Video Technol
4. Dinh VN, Phuong HA, Duc DV, Ha PTK, Tien PV, Thang NV (2006) High speed SAD architecture for variable block size motion estimation in HEVC encoder. In: IEEE sixth international conference on communications and electronics (ICCE). Vietnam pp 195–198
5. Silveira B, Paim G, Abreu B, Grellert M, Diniz CM, Ceśar da Costa EA, Bampi S (2017) Power-efficient sum of absolute differences hardware architecture using adder compressors for integer motion estimation design. IEEE Trans Circ Syst I: Regul Papers 64(12):3126–3137
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