Power Optimization of a 32-Bit ALU Using Distributed Clock Gating Technique
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Publisher
Springer Singapore
Link
http://link.springer.com/content/pdf/10.1007/978-981-15-5558-9_71
Reference10 articles.
1. Castro J, Parra P, Acosta AJ (2010) Optimization of clock-gating structures for low-leakage high-performance applications. Proceedings of IEEE international symposium on efficient embedded computing. pp. 3220–3223
2. Shinde J, Salankar SS (2011) Clock gating-A power optimizing technique for VLSI circuits. Annual IEEE India conference (INDICON). pp. 1–4
3. Kathuria J, AyouKhan M, Noor A (Aug 2011) A review of clock gating technique. MIT Int J Electron Commmun Eng 1(2)
4. Kamaraju M, Lal Kishore K, Tilak AVN (December 2010) Power optimized ALU efficient datapath. Int J Comput Appl 11(11)
5. Pandey B, Pattanaik M (2013) Clock gating aware low power ALU design and implementation on FPGA. 2nd Int Conf Network Comput Sci (ICNCS), Singap April 1–2
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