Routing of Flits in Parallel Input Interface Scenario in a Generalized Network-On-Chip Framework Using Wormhole Flow Control Algorithm-Reference-Cited by-同舟云学术

Routing of Flits in Parallel Input Interface Scenario in a Generalized Network-On-Chip Framework Using Wormhole Flow Control Algorithm

Published:2021-12-01 Issue: Volume: Page:679-693
ISSN:1876-1100
Container-title:Emerging Research in Computing, Information, Communication and Applications
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Author:

Uma R.,Sarojadevi H.,Sanju V.

Publisher

Springer Singapore

Link

https://link.springer.com/content/pdf/10.1007/978-981-16-1342-5_52

Reference12 articles.

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2. Hemani A, Jantsch A, Kumar S, Postula A, Öberg J, Milberg M, Lindqvist D (2001) Network on a chip: an architecture for billion transistor era. DAC 2001

3. Bjerregaard T, Mahadevan S (2006) A survey of research and practices of network on-chip. ACM Computing Survey March 2006

4. Rantala V, Lehtonen T, Plosila J (2006) Network on chip routing algorithms. TUCS Technical Report No 779, August 2006

5. Ali M, Welzl M, Zwicknagl M (2008) Networks on chips: scalable interconnects for future systems on chips. In: 4th European conference on circuits and systems for communications. 03 September 2008

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