Author:
Sai Vamsi Chilukuri,Aravind Kasyap Sanagaram,Saiprateeka S.,Agrawal Sonali
Reference15 articles.
1. Kin NS et al (2003) Leakage current: Moore’s law meets static power. IEEE Comput 36(12):68–75
2. Mohankumar N, Ravikumar RV, Paramasivan D, Ramya H, Raghavan R (2014) Low power fault-tolerant reversible full adders. In: International conference on communication and computing (ICC2014)
3. Hassoune I, Flandore D, O’Connor I, Legat JD (2010) ULPFA: A new efficient design of a power-aware full adder. IEEE Trans Circ Syst I, Reg Papers 57(8):2066–2074
4. Wairya S, Nagaria RK, Tiwari S (2008) New design methodologies for high-speed low-voltage 1-bit CMOS full adder circuits. Int J Elect Circ Syst 2(4):217–223
5. Alioto M, Paulumbo G (2002) Analysis and comparison on full adder block in submicron technology. IEEE transactions on very large-scale integration (VLSI) systems 10(6):806–823