Automation of Translating Unit-Level Verification Scenarios for Test Vector Generation of SoC-Reference-Cited by-同舟云学术

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Automation of Translating Unit-Level Verification Scenarios for Test Vector Generation of SoC

Published:2022 Issue: Volume: Page:527-536
ISSN:2367-3370
Container-title:Intelligent Sustainable Systems
language:
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Author:

Anilkumar Rahul,Varaprasad B. K. S. V. L.,Padmapriya K.

Publisher

Springer Nature Singapore

Link

https://link.springer.com/content/pdf/10.1007/978-981-16-6309-3_50

Reference20 articles.

1. Yun, Y.-N., et al.: Beyond UVM for practical SoC verification. In: International SoC Design Conference, pp. 158–162. Jeju, Korea (South) (2011)

2. Wang, J., et al.: A UVM verification platform for RISC-V SoC from module to system level. In: IEEE 5th International Conference on Integrated Circuits and Microsystems, pp. 242–246. Nanjing, China (2020)

3. Salah, K.: A UVM-based smart functional verification platform: concepts, pros, cons, and opportunities. In: 9th International Design and Test Symposium, pp. 94–99. Algeries, Algeria (2014)

4. Subramanyan, P., et al.: Template-based parameterized synthesis of uniform instruction-level abstractions for SoC verification. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37(8), pp. 1692–1705 (2018)

5. El-Ashry, S., et al.: On error injection for NoC platforms: a UVM-based generic verification environment. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 39(5), 1137–1150 (2019)

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Verification of an ARM Cortex-M3 based SoC using UVM;2023 10th International Conference on Signal Processing and Integrated Networks (SPIN);2023-03-23

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