Adiabatic SRAM Cell and Array

Author:

Manna Ayon,Kanchana Bhaaskaran V. S.

Publisher

Springer Singapore

Reference8 articles.

1. Kanchana Bhaaskaran, V.S. 2011. Energy recovery performance of quasi adiabatic circuits using lower technology nodes. In India international conference on power electronics 2010 (IICPE2010), 1–7, New Delhi.

2. Nakata, S., T. Kusumuto, M. Miyama, and Y. Matsuda. 2009. Adiabatic SRAM with a large margin of VT variation by controlling the cell power line and word line voltage. In Proceedings ISCAS digest, 393–396.

3. Kanchana Bhaaskaran, V.S., S. Salivahanan, and D.S. Emmanuel. 2006. Semi-custom design of adiabatic adder circuits. In Proceedings of 19th international conference on VLSI design and embedded systems design, 745–748.

4. Hu, J., H. Li, and H. Dong. 2005. A low-power adiabatic register file with two types of energy-efficient line drivers. In 48th Midwest symposium on circuits and systems, 1753–1756.

5. Hu, J.P., X.Y. Feng, J.J. Yu, and Y.S. Xia. 2004. Low power dual transmission gate adiabatic logic circuits and design of SRAM. In 47th Midwest symposium on circuits and systems, 565–568.

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