6T SRAM Cell Design and Investigation for Ultra-Low-Power Application
Author:
Publisher
Springer Singapore
Link
http://link.springer.com/content/pdf/10.1007/978-981-13-0776-8_49
Reference12 articles.
1. Giraud B, Amara A, Thomas O (2010) An innovative 6T hybrid SRAM cell in sub-32 nm double-gate MOS technology. In: Fifth IEEE international symposium on electronic design, test and application
2. Kursan V, Friedman EG (2006) Multi-voltage CMOS circuit design. Wiley Ltd., ISBN 0-470-01023-1
3. Liu Z (2008) Multi-voltage nanoscale CMOS circuit techniques. Ph. D. thesis, University of Wisconsin, Madison
4. Jiao H et al (2016) Low power and robust memory circuits with asymmetrical ground gating. Microelectron J 48:109–119
5. Azam T (2010) Robust asymmetric 6T-SRAM cell for low-power operation in nano-CMOS technologies. Electron Lett 46(4):273–274
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