Author:
Halder Saurabh,Saha Mihir Lal,Malvika ,Talukdar Jagritee,Mummaneni Kavicharan
Publisher
Springer Nature Singapore
Reference17 articles.
1. P. Gowthami, R.V.S. Satyanarayana, Design of an efficient multiplier using Vedic mathematics and reversible logic, in IEEE International Conference on Computational Intelligence and Computing Research (ICCIC) (2016), pp. 1–4. https://doi.org/10.1109/ICCIC.2016.7919603
2. Anamika, R. Bhardwaj. Reversible logic gates and its performances, in 2nd International Conference on Inventive Systems and Control (ICISC) (2018), pp. 226–231. https://doi.org/10.1109/ICISC.2018.8399068
3. C.H. Bennett, Logical reversibility of computation. IBM J. Res. Dev. 17(6), 525–532 (1973). https://doi.org/10.1147/rd.176.0525
4. H. Thapliyal, N. Ranganathan, Design of efficient reversible binary subtractors based on a new reversible gate, in IEEE Computer Society Annual Symposium on VLSI (2009), pp. 229–234. https://doi.org/10.1109/ISVLSI.2009.49
5. B. Raghu Kanth, B. Murali Krishna, M. Sridhar, V.G. Santhi Swaroop. A distinguish be- tween reversible and conventional logic GATES. Int. J. Eng. Res. Appl. (IJERA) 2(2), 148–151 (2012)