Efficient methods for formally verifying safety properties of hierarchical cache coherence protocols-Reference-Cited by-同舟云学术

Efficient methods for formally verifying safety properties of hierarchical cache coherence protocols

Published:2010-02 Issue:1 Volume:36 Page:37-64
ISSN:0925-9856
Container-title:Formal Methods in System Design
language:en
Short-container-title:Form Methods Syst Des

Author:

Chen Xiaofang,Yang Yu,Gopalakrishnan Ganesh,Chou Ching-Tsun

Publisher

Springer Science and Business Media LLC

Subject

Hardware and Architecture,Theoretical Computer Science,Software

Link

http://link.springer.com/content/pdf/10.1007/s10703-010-0092-y.pdf

Reference41 articles.

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4. Barroso LA, Gharachorloo K, McNamara R, Nowatzyk A, Qadeer S, Sano B, Smith S, Stets R, Verghese B (2000) Piranha: a scalable architecture based on single-chip multiprocessing. In: Int’l symposium on computer architecture

5. Baskett F, Jermoluk TA, Solomon D (1988) The 4d-mp graphics superworkstation: computing + graphics = 40 mips + 40 mflops and 100,000 lighted polygons per second. In: Digest of papers, thirty-third IEEE computer society int’l conference, pp 468–471

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