Efficient and flexible memory architecture to alleviate data and context bandwidth bottlenecks of coarse-grained reconfigurable arrays

Author:

Yang Chen,Liu LeiBo,Yin ShouYi,Wei ShaoJun

Publisher

Springer Science and Business Media LLC

Subject

General Physics and Astronomy

Reference34 articles.

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2. Bigdeli A, Biglari-Abhari M, Leung S H S, et al. Multimedia extensions for a reconfigurable processor. In: Proceedings of International Symposium on Intelligent Multimedia, Video and Speech Processing, Hong Kong, China, 20–22 Oct. 2004. 426–429

3. Singh H, Lee M H, Lu G M, et al. Morphosys: An integrated reconfigurable system for data-parallel and compute intensive applications. IEEE Trans Comput, 2000, 49: 456–481

4. Mei B F, Vernalde S, Verkest D, et al. ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix. In: Proceedings of IEEE International Conference on Field Programmable Logic and Applications, Lisbon, Portugal, 2003. 61–70

5. Ganesan M K A, Singh S, May F, et al. H. 264 decoder at HD resolution on a coarse grain dynamically reconfigurable architecture. In: Proceedings of IEEE International Conference on Field Programmable Logic and Applications, Amsterdam, Netherlands, 2007. 467–471

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