Author:
Meyer Brett H.,Thomas Donald E.
Publisher
Springer Science and Business Media LLC
Subject
Hardware and Architecture,Software
Reference17 articles.
1. Guo J, Papanikolaou A, Marchal P, Catthoor F (2006) Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture. In: SLIP ’06
2. Lahiri K, Raghunathan A, Dey S (2000) Efficient exploration of the SoC communication architecture design space. In: ICCAD ’00
3. Hu J, Deng Y, Marculescu R (2002) System-level point-to-point communication synthesis using floorplanning information. In: ASP-DAC ’02
4. Maguerdichian S, Drinic M, Kirovski D (2001) Latency-driven design of multi-purpose systems-on-chip. In: DAC ’01
5. Thepayasuwan N, Doboli A (2005) Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed. IEEE Trans. VLSI 13(5)