Author:
Chen Kun-Chih,Lin Shu-Yen,Shen Wen-Chung,Wu An-Yeu
Publisher
Springer Science and Business Media LLC
Subject
Hardware and Architecture,Software
Reference20 articles.
1. Benini L, Micheli GD (2002) Network on chip: a new paradigm for systems on chip design. In: IEEE proceedings of the conference on design, automation and test in Europe conference and exhibition, pp 418–419
2. Semiconductor Association (2005) The international technology roadmap for semiconductor (ITRS)
3. Petersen K, Oberg J (2007) Toward a scalable test methodology for 2D mesh network-on-chips. In: Proceedings of the conference on design, automation and test in Europe (DATE ’07), pp 367–372
4. Grecu C, Pande P, Ivanov A, Saleh R (2006) BIST for network-onchip interconnect infrastructures. In: Proceedings of 24th IEEE VLSI test symposium, April, 2006, pp 30–35
5. Lin S-Y, Shen W-C, Hsu C-C, Chao C-H, Wu A-Y (2009) Fault-tolerant router with built-in self-test/self-diagnosis and fault-isolation circuits for 2D-mesh based chip multiprocessor systems. In: Proc IEEE int symp VLSI design, automation, and test (VLSI-DAT-2009), pp 72–75
Cited by
6 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献