1. Leverich J, Arakida H, Solomatnikov A, Firoozshahian A, Horowitz M, Kozyrakis C (2007) Comparing memory systems for chip multiprocessors. In: ISCA ’07: proceedings of the 34th annual international symposium on computer architecture. ACM, New York, pp 358–368
2. Kongetira P, Aingaran K, Olukotun K (2005) Niagara: a 32-way multithreaded sparc processor. Micro IEEE 25:21–29
3. Barroso LA, Gharachorloo K, McNamara R, Nowatzyk A, Qadeer S, Sano B, Smith S, Stets R, Verghese B (2000) Piranha: a scalable architecture based on single-chip multiprocessing. In: ISCA ’00: proceedings of the 27th annual international symposium on computer architecture. ACM, New York, pp 282–293
4. Archibald J, Baer J-L (1986) Cache coherence protocols: evaluation using a multiprocessor simulation model. ACM Trans Comput Syst 4(4):273–298
5. Agarwal A, Simoni R, Hennessy J, Horowitz M (1988) An evaluation of directory schemes for cache coherence. In: ISCA ’88: proceedings of the 15th annual international symposium on computer architecture. IEEE Computer Society, Los Alamitos, pp 280–298