Minimization of CNTFET Ternary Combinational Circuits Using Negation of Literals Technique-Reference-Cited by-同舟云学术

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Minimization of CNTFET Ternary Combinational Circuits Using Negation of Literals Technique

Published:2014-05-24 Issue:6 Volume:39 Page:4875-4890
ISSN:1319-8025
Container-title:Arabian Journal for Science and Engineering
language:en
Short-container-title:Arab J Sci Eng

Author:

Sridevi V.,Jayanthy T.

Publisher

Springer Science and Business Media LLC

Subject

Multidisciplinary

Link

http://link.springer.com/content/pdf/10.1007/s13369-014-1147-y.pdf

Reference31 articles.

1. Mukaidono, M.: Regular ternary logic functions—ternary logic functions suitable for treating ambiguity. IEEE Trans. Comput. C-35(2), 179–183 (1986)

2. Smith, K.C.: The prospects for multivalued logic: a technology and applications view. IEEE Trans. Comput. C-30, 619–634 (1981)

3. Hurst, S.L.: Multivalued logic—its status and its future. IEEE Trans. Comput. C-33, 1160–1179 (1984)

4. Balla, P.C.; Antoniou, A.: Low power dissipation MOS ternary logic family. IEEE J. Solid State Circuits 19(5), 739–749 (1984)

5. Rich, D.A.: A survey of multivalued memories. IEEE Trans. Comput. 35(2), 99–106 (1986)

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