Author:
Durgesh Nandan ,Kanungo Jitendra,Mahajan Anurag
Publisher
Springer Science and Business Media LLC
Reference33 articles.
1. Abid Z, El-Dib Dalia A, Mudassir R (2016) Modified operand decomposition multiplication for high performance parallel multipliers. J Circuits Syst Comput 25(12):1–12
2. Agrawal RK, Kittur HM (2013) ASIC based logarithmic multiplier using iterative pipelined architecture. In: IEEE conference on information and communication technologies, pp 362–366
3. Babic Z, Avramovic A, Bulic P (2011) An iterative logarithmic multiplier. Microprocess Microsyst 35(1):23–33
4. Basu M (2002), Gaussian-based edge-detection methods—a survey. IEEE Trans Syst Man Cybern Part C Appl Rev 32(3):252–260
5. Bulic P, Babic Z, Avramovic A (2010) A simple pipelined logarithmic multiplier. In: IEEE international conference on computer design (ICCD), pp 235–240
Cited by
16 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献