Design and analysis of low power 8-bit ALU on reversible logic for nanoprocessors

Author:

Amirthalakshmi T. M.,Raja S. Selvakumar

Publisher

Springer Science and Business Media LLC

Subject

General Computer Science

Reference39 articles.

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3. Bommi RM (2016) Circuit design and CNTFET implementation of ultra adder. Austral J Basic Appl Sci 10(1):214–218

4. Deng G, Chen C (2013) Binary multiplication using hybrid MOS and multi-gate single-electron transistors. IEEE Trans Very Large Scale Integr (VLSI) Syst 21(9):1573–1582

5. Dhulipalla L, Deepak A (2011) Design and implementation Of 4-bit ALU using FINFETS for nano scaletechnology. In: IEEE international conference on nanoscience, engineering and technology, pp 190–195; https://doi.org/10.1109/ICONSET.2011.6167951

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1. Comparative Energy & Hardware Analysis on Implementation of 8-Bit ALU Using Different FPGAs Families;2023 6th International Conference on Contemporary Computing and Informatics (IC3I);2023-09-14

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5. A novel reversible ternary coded decimal adder/subtractor;Journal of Ambient Intelligence and Humanized Computing;2020-09-01

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