An integrated partitioning and synthesis system for dynamically reconfigurable Multi-FPGA architectures-Reference-Cited by-同舟云学术

An integrated partitioning and synthesis system for dynamically reconfigurable Multi-FPGA architectures

Published:1998 Issue: Volume: Page:31-36
ISSN:0302-9743
Container-title:Lecture Notes in Computer Science
language:
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Author:

Ouaiss Iyad,Govindarajan Sriram,Srinivasan Vinoo,Kaul Meenakshi,Vemuri Ranga

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/3-540-64359-1_669.pdf

Reference8 articles.

1. M. Vasilko and D. Ait-Boudaoud, “Architectural Synthesis Techniques for Dynamically Reconfigurable Logic”, FPL'96.

2. M. Vootukuru, R. Vemuri, and N. Kumar, “Resource Constrained RTL Partitioning for Synthesis of Multi-FPGA Designs”, Proceedings of the 10th International Conference on VLSI Design, IEEE Press, 12 pages, 140–144, January 1997.

3. M. Kaul and R. Vemuri, “Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures”, to appear in Design, Automation, and Test in Europe, February 98.

4. Holland J., “Adaptation in Natural and Artificial Systems”, Ann Arbor: University of Michigan Press, 1975.

5. Ram Vemuri, “Genetic Algorithms for Partitioning, Placement, and Layer Assignment for Multichip Modules”, PhD thesis, University of Cincinnati, USA, July 1994.

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