Reliable S-Box Hardware Implementation by Gate-Level Fault Masking Enhancement
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Computer Science Applications,Energy Engineering and Power Technology,Control and Systems Engineering
Link
http://link.springer.com/article/10.1007/s40313-019-00441-6/fulltext.html
Reference34 articles.
1. Ahmad, N., Hasan, R., & Jubadi, W. M. (2010). Design of AES S-box using combinational logic optimization. In IEEE symposium on industrial electronics and applications (pp. 696–699). https://doi.org/10.1109/ISIEA.2010.5679375.
2. Ahmad, N., & Hasan, S. M. R. (2013). Low-power compact composite field AES S-box/Inv S-box design in 65 nm CMOS using novel XOR gate. Integration the VLSI Journal, 46(4), 333–344. https://doi.org/10.1016/j.vlsi.2012.06.002 .
3. Albayrak, G., & Albayrak, U. (2016). Investigation of ready mixed concrete transportation problem using linear programming and genetic algorithm. Civil Engineering Journal, 2(10), 491–496.
4. Almukhaizim, S., & Makris, Y. (2008). Soft error mitigation through selective addition of functionally redundant wires. IEEE Transactions on Reliability, 57(1), 23–31. https://doi.org/10.1109/TR.2008.916877 .
5. Ansari, M. S., Mahani, A., & Mohammadi, K. (2016). Low power modular redundancy: A power efficient fault tolerant approach for digital circuits. COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering, 35(3), 1098–1106. https://doi.org/10.1108/COMPEL-08-2015-0266 .
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