FPGA Implementation of a Prototype Hierarchical Control Network for Large-Scale Signal Processing Applications

Author:

Lemaitre Jérôme,Deprettere Ed

Publisher

Springer Berlin Heidelberg

Reference18 articles.

1. Bhattacharya, B., Bhattacharyya, S.: Parameterized Dataflow Modeling of DSP Systems. In: Proc. of the Intl. Conf. on Acoustics, Speech, and Signal Processing (ASSP 2000), Istanbul, Turkey (June 2000)

2. Bhattacharya, B., Bhattacharyya, S.: Quasi-static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems. In: Proc. of the Intl. Workshop on Rapid System Prototyping (RSP 2000), Paris, France (June 2000)

3. Strehl, K., Thiele, L., Gries, M., Ziegenbein, D., Ernst, R., Teich, J.: FunState - An Internal Design Representation for Codesign. IEEE Trans. on VLSI Systems (2001)

4. Nikolov, H., Stefanov, T., Deprettere, E.: Modeling and FPGA Implementation of Applications using Parameterized Process Networks with Non-Static Parameters. In: Proc. of the Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), Napa, California, USA (April 2005)

5. Rutten, M., Pol, E.-J., van Eijnhoven, J., Walters, K., Essink, G.: Dynamic reconfiguration of streaming graphs on a heterogeneous multiprocessor architecture. In: SPIE Electronic Imaging: Embedded processors for Multimedia and Communications II, San Jose, CA, USA, January, vol. 5683 (2005)

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