A chip set for pipeline and parallel pipeline FFT architectures

Author:

Szwarc V.,Desormeaux L.,Wong W.,Yeung C. P. S.,Chan C. H.,Kwasniewski T. A.

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Information Systems,Signal Processing

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Mathematical modelling for the design of DFT processor using resource sharing;1ST INTERNATIONAL CONFERENCE ON MATHEMATICAL TECHNIQUES AND APPLICATIONS: ICMTA2020;2020

2. A 64-Point Fourier Transform Chip for High-Speed Wireless LAN Application Using OFDM;IEEE Journal of Solid-State Circuits;2004-03

3. A pipelined architecture for the multidimensional DFT;IEEE Transactions on Signal Processing;2001

4. An orthogonal time-frequency extraction approach to 2D systolic architecture for 1D DFT computation;The Journal of VLSI Signal Processing;1999

5. VLSI configurable delay commutator for a pipeline split radix FFT architecture;IEEE Transactions on Signal Processing;1999

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