Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures
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Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/11556930_68
Reference28 articles.
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2. HardCopy Series Handbook, Altera Inc. (2005), http://www.altera.com
3. Chen, D., Cong, J., Li, F., He, L.: Low-Power Technology Mapping for FPGA Architectures with Dual Supply Voltages. In: Proceedings of ACM/SIGDA International Symposium on Field-programmable Gate Arrays (2004)
4. Alexander, M.J.: Power Optimization for FPGA Look-up Tables. In: Proceedings of ACM 1997 International Symposium on Physical Design, pp. 156–162 (1997)
5. Vuilled, P., Benini, L., DeMicheli, G.: Re-Mapping for Low Power Under Tight Timing Constraints. In: ISPLED 1997, August 1997, pp. 156–162 (1997)
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