Author:
Brzozowski Ireneusz,Kos Andrzej
Publisher
Springer Berlin Heidelberg
Reference8 articles.
1. Roy, K., Mukhopadhyay, S., Mahmoodi-Meimand, H.: Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits. Proceedings of the IEEE 91(2), 305–327 (2003)
2. Wang, Q., Vrudhula, S.B.K., Yeap, G., Gangulu, S.: Power Reduction and Power-Delay Trade-Offs Using Logic Transformations. ACM Trans. On Design Automation of Electronic Systems 4(1), 97–121 (1999)
3. Iman, S., Pedram, M.: Logic Synthesis for Low Power VLSI Designs. Kluwer, Boston (1998)
4. Tseng, J.-M., Jou, J.-Y.: Two-Level Logic Minimization for Low Power. ACM Trans. On Design Automation of Electronic Systems 4(1), 52–69 (1999)
5. Theodoridis, G., Theoharis, S., Soudris, D., Goutis, C.: A New Method for Low Power Design of Two-Level Logic Circuits. VLSI Design Journal of Custom-Chip Design, Simulation, and Testing 9(2), 147–158 (1999)
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