Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers
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Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/11556930_52.pdf
Reference12 articles.
1. Kourtev, S., Friedman, E.G.: Timing Optimization Through Clock Skew Scheduling. Kluwer Academic Publishers, Norwell (2000)
2. Sauter, S., Schmitt-Landsiedel, D., Thewes, R., Weber, W.: Effect of parameter variations at chip and wafer level on clock skews. IEEE Transactions on Semiconductor Manufacturing 13(4), 395–400 (2000)
3. Natarajan, S., Breuer, M.A., Gupta, S.K.: Process variations and their impact on circuit operation. In: Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November 1998, pp. 73–81 (1998)
4. Tang, K.T., Friedman, E.G.: Delay and noise estimation of cmos logic gates driving coupled rc interconnections. Integration, the VLSI Journal 29(2), 131–165 (2000)
5. Velenis, D., Papaefthymiou, M.C., Friedman, E.G.: Reduced delay uncertainty in high performance clock distribution networks. In: Proceedings of the IEEE Design Automation and Test in Europe Conference, March 2003, pp. 68–73 (2003)
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