Optimizing transistor networks using a graph-based technique

Author:

Possani Vinicius N.,de Souza Renato S.,Domingues Julio S.,Agostini Luciano V.,Marques Felipe S.,da Rosa Leomar S.

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Reference22 articles.

1. Brayton, R. K. (1987). Factoring logic functions. IBM Journal of Research and Development, 31(2), 187–198.

2. Mintz, A., & Golumbic, M. C. (2005). Factoring Boolean functions using graph partitioning. Discrete Applied Mathematics, 149(1–3), 131–153.

3. Golumbic, M. C., Mintz, A., & Rotics, U. (2008). An improvement on the complexity of factoring read-once Boolean functions. Discrete Applied Mathematics, 156(10), 1633–1636.

4. Yoshida, H., Ikeda, M., & Asada, K (2006). Exact minimum logic factoring via quantified Boolean satisfiability. In International conference on electronics, circuits, and systems (pp. 1065–1068). Venice: ICECS.

5. Dietmeyer, D. L. (1971). Logic design of digital systems. Needham Heights: Allyn and Bacon.

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