A Novel Reliability Assessment Scheme for Nano Resistive Random Access Memory (RRAM) Testing
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s10470-022-02007-0.pdf
Reference52 articles.
1. Yakopcic, C., Hasan, R., & Taha, T. M. Hybrid crossbar architecture for a memristor based cache. Microelectronics Journal. 2015 Nov 1;46(11):1020-32. DOI: https://doi.org/10.1109/NAECON.2014.7045809
2. Zackriya, M., Kittur, H. M., & Chin, A. A novel read scheme for large size one-resistor resistive random access memory array.Scientific reports. 2017 Feb10;7:42375. DOI: https://doi.org/10.1038/srep42375
3. Chen, C. Y., Shih, H. C., Wu, C. W., Lin, C. H., Chiu, P. F., Sheu, S. S., & Chen, F. T. RRAM defect modeling and failure analysis based on march test and a novel squeeze-search scheme.IEEE Transactions on Computers. 2014 Jan27;64(1):180–90. DOI: https://doi.org/10.1109/TC.2014.12
4. Hongal, V. A., Kotikalapudi, R., Kim, Y. B., & Choi, M. A novel “Divide and Conquer” testing technique for memristor based lookup table. In 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS) 2011 Aug 7 (pp. 1–4). IEEE. DOI: https://doi.org/10.1109/MWSCAS.2011.6026406
5. Li, H., Gao, B., Chen, Z., Zhao, Y., Huang, P., Ye, H. … Kang, J. (2015 Aug). A learnable parallel processing architecture towards unity of memory and computing. Scientific reports, 14, 5:13330. DOI: https://doi.org/10.1038/srep13330
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