A 0.6 V 100 KS/s 8–10 b resolution configurable SAR ADC in 0.18 μm CMOS

Author:

Zhu Zhangming,Xiao Yu,Wang Weitie,Wang Qiyu,Yang Yintang

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Reference12 articles.

1. Pieter, H., & Yan, Z., et al. (2012) A 7-to-10 b 0-to-4 MS/s Flexible SAR ADC with 6.5-to-16 fJ/conversion-step. In IEEE Journal of Solid-State Circuits Conference (pp. 472–473).

2. Lee, S.-K., et al. (2011). A 21 fJ/conversion-step 100 KS/s 10-bit ADC with a low-noise time-domain comparator for low-power sensor interface. IEEE Journal of Solid-State Circuits, 46(3), 651–659.

3. Verma, N., & Chandrakasan, A. P. (2007). An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes. IEEE Journal of Solid-State Circuit, 42(6), 1196–1204.

4. Sakurai, T., Kawaguchi, H., & Kuroda, T. (1997). Low-power CMOS design through VT control and low-swing circuits. In Proceedings of international symposium on low power electron design (pp. 1–6).

5. Abo, A. M., & Gray, P. R. (1999). A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE Journal of Solid-State Circuit, 34(3), 599–606.

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